1. Field of the Invention
The present invention relates to a pixel structure and a manufacturing method of a liquid crystal display (LCD) and, more particularly, to a pixel structure for reducing a parasitic capacitance (Cpd), and to a method for manufacturing thereof.
2. Description of the Prior Art
Liquid crystal displays (LCDs) have become highly popular display devices on the technology market as they have a small volume and low divergence. The aperture ratio of the pixel structures in an LCD manufacturing process influences the utilization of a back light module that in turn influences the brightness of the LCD. Therefore, how to increase the aperture ratio of the pixel structure is an important direction of LCD research.
In general, the major factor influencing the aperture ratio of the pixel structure is the width between a pixel electrode and a data line. When the pixel electrode is too close to the data line, a different voltage from the data line before the next frame will influence the holding voltage of the pixel electrode. That will result a cross talk issue and decrease the quality of the LCD.
Referring to FIG. 1 schematically illustrates the pixel structure of the prior art. An array structure of an LCD has a thin film transistor (TFT) 102, a plurality of data lines 104 that are parallel with each other, and a plurality of scan lines 106 that are parallel with each other. The data lines 104 cross the scan lines 106 to define a plurality of pixel structure 108. Each of the plurality of pixel structure 108 has a pixel electrode 110, and a shielding electrode 112 under the pixel electrode 110.
Referring to FIG. 2 schematically illustrates the cross section view of FIG. 1 along the line AA′. As FIG. 2 shows, the shielding electrode 112 is covered by an insulating layer such as a gate insulating layer 122. The data line 104 disposes on the gate insulating layer 122 and disposes between the two shielding electrodes 112. The gate insulating layer 122 and the data line 104 are covered by a passivation layer 124. The pixel electrode 110 disposes on the passivation layer 124. The parasitic capacitance (Cpd) being disposes between the pixel electrode 110 and the data line 104 is one factor influencing the crosstalk. The storage capacitance (Cst) 128 includes the pixel electrode 110, the passivation layer 124, the gate insulating layer 122, and the shielding electrode 112.
In the prior art, the data line and the pixel electrode have a fixed width in order to decrease the Cpd. As the width between the data line and the pixel electrode becomes wider, and the aperture ratio becomes lower, the utilization of the back light module decreases. Another method to decrease the effect of Cpd is by increasing the ratio of the storage capacitance to decrease the ratio of the Cpd divided by the total capacitances. In general, increasing the overlapped area between the two electrodes of the storage capacitance can achieve this result. In general manufacture, however, one electrode of the storage capacitance is usually made by an opaque metal layer. To increase the storage capacitance by adding overlapped area will decrease the aperture ratio of the pixel structure.